Lead Image © Wayne Daniels, 123RF.com

Lead Image © Wayne Daniels, 123RF.com

Boosting Performance with Intel’s QuickAssist Technology

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Article from ADMIN 33/2016
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Quickassist technology offloads computationally intensive compression and encryption tasks to provide a performance boost for Intel processors.

Big Data, IoT, and storage (cloud and enterprise) solutions are very compute-intensive. These technologies move large amounts of data in and out of storage and require secure data transmission across the network. To help this evolving market, Intel is introducing QuickAssist technology.

Intel QuickAssist Technology [1] provides security and compression acceleration capabilities to improve performance and efficiency on Intel Architecture platforms. Server, networking, big data, and storage applications use Intel QuickAssist to offload compute-intensive operations, such as:

  • Symmetric cryptography functions, including cipher operations and authentication operations
  • Public key functions, including RSA, Diffie-Hellman, and elliptic curve cryptography,
  • Compression and decompression functions, including DEFLATE

QuickAssist enables users to meet the demands of ever-increasing amounts of data, especially data with the need for encryption and compression. QuickAssist helps users ensure applications are fast, secure, and available.

What is QuickAssist?

Intel QuickAssist Technology runs on Intel architecture. At a high level, the platform pairs an Intel architecture processor(s) with the Intel Communications 8925 to 8955 Series chipset.

QuickAssist offloads crypto and compression tasks from the CPU to the 89XX communications chip. Functionally, the Intel Communications Chipset 8925 to 8955 is most easily described as a Platform Controller Hub (PCH) that includes both standard PC interfaces (e.g., PCI Express, SATA, USB, and so on) together with Intel QuickAssist Technology accelerator and I/O interfaces.

Figure 1 shows an Intel communications platform that features the Intel Xeon Processor E5-2658 and E5-2448L with the Intel Communications Chipset 89xx Development Kit.

Figure 1: Intel communication platform equipped with the 89xx chipset.

The Intel QuickAssist accelerator on the 89XX chip acts as a companion chip to the CPU. Its purpose is to relieve the CPU from compute-intensive operations such as cryptography and compression operations. The acceleration capabilities provide security and compression services that improve performance and efficiency in storage, networking, big data, and security applications.

Intel QuickAssist in the Software Stack

Application developers can access QuickAssist features through the Intel QuickAssist API. The API enables easy interfacing between the customer application and the QuickAssist acceleration driver.

It is also possible to use QuickAssist with open source software frameworks via a SHIM layer. The SHIM layer acts as an adapter between the Intel QuickAssist API and the interface expected by industry standard frameworks. Figure 2 shows how you can integrate Intel QuickAssist Technology at multiple levels.

Figure 2: Intel QuickAssist technology integrated at multiple levels.

The QuickAssist API accesses the Intel QuickAssist driver, which is responsible for exposing the acceleration services to the application software. The driver consists of two layers:

  • The Acceleration Driver Framework (ADF)
  • The Service Access Layer (SAL)

The Acceleration Driver Framework has multiple roles, including:

  • Downloading the firmware that will control the hardware performing the acceleration operations. The firmware will convert request messages created by SAL into commands that control the acceleration engines. When the acceleration operation completes, it will send a response message back.
  • Creating the Transmit and Receive rings. The Acceleration Driver Framework communicates with the firmware through host DRAM implemented rings. The ring system is used to pass request or response messages between the SAL and the firmware.
  • Listening and responding to PCIe events.
  • Adding debugging capability via the proc filesystem. It is possible to view the configuration and the ring traffic activity using an entry in the proc filesystem. The following console command will show the configuration of the device:
cat /proc/icp_dh895xcc_dev0/cfg_debug
  • Handle the user configuration defined in the configuration file.

The Service Access Layer (SAL) in turn creates and starts the acceleration services. Two services are currently available:

  • The cryptographic service
  • The compression service

Once a service is enabled, the SAL will enable the service-associated APIs. The SAL will also create the messages that will be put on the transmit rings. When a transmit message is processed, the firmware will put a response message on the receive rings. When a response message is present on the receive ring, SAL will decode the response message in a callback function and update the API output parameters with statistics and processed payload. Figure 3 shows the QuickAssist driver architecture.

Figure 3: Intel QuickAssist driver architecture.

Intel QuickAssist API

The Intel QuickAssist API is the top-level API for QuickAssist technology. The API can operate both in kernel and user space and contains structures, data types, and definitions that are common across the interface. The application must format the payload data in either Flat buffer or Scatter-Gather buffer list. The two data structures are described in Table 1:

Table 1

QuickAssist API Buffer Format

Buffer Option Example Diagram
Flat buffer format struct _CpaFlatBuffer { Cpa32U dataLenInBytes; Cpa8U *pData;} CpaFlatBuffer;
Scatter Gather buffer list format struct _CpaBufferList { Cpa32U numBuffers; CpaFlatBuffer *pBuffers; void *pUserData; void *pPrivateMetaData;} CpaBufferList;

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