18%
20.03.2023
.exe
QUAD_MPI
FORTRAN90/MPI version
Estimate an integral of f(x) from A to B.
f(x) = 50 / (pi * ( 2500 * x * x + 1 ) )
A = 0.00000
B = 10.0000
N = 9999999
18%
02.08.2021
public key has been saved in eks-ssh.pub.
09 The key fingerprint is:
10 SHA256:Pidrw9+MRSPqU7vvIB7Ed6Al1U1Hts1u7xjVEfiM1uI
11 The key's randomart image is:
12 +---[RSA 4096]----+
13 | .. ooo+|
14
18%
30.05.2021
A long time ago, I was a system administrator for a couple of HPC systems, but I also inherited two Hewlett-Packard (HP) N-class servers (mainframes). Along with two WORM storage units, these were
18%
10.04.2015
.org
Tutanota
ProtonMail
Mailbox from EUR1
Yes/2GB
Yes/2GB
Free/1GB
Free/500MB
Storage space expansion
Yes
Yes
Yes
Currently
18%
09.10.2017
as input. This procedure is described in detail at the CNI GitHub repository [9].
Calico Project
Calico [3] considers the ratio of nodes to containers. The idea is to transfer the concepts and relations
18%
05.12.2014
/home/chris/.cache/software-center/piston-helper/software-center.ubuntu.\
com,api,2.0,applications,en,ubuntu,precise,\
amd64,,bbc2274d6e4a957eb7ea81cf902df9e0:
"description": "La revista
18%
18.06.2014
]: 13502 ( 3.48%) ( 87.59% cumulative)
[ 64- 128 KB]: 12083 ( 3.11%) ( 90.70% cumulative)
[ 128- 256 KB]: 8623 ( 2.22%) ( 92.93% cumulative)
[ 256- 512 KB]: 13437 ( 3
18%
14.01.2016
the registers and main memory, Level 1 (L1), Level 2 (L2), and even L3 and L4 caches have been added. Typically the L1 cache is part of the processor (each core) and can store more data than the registers
18%
03.12.2015
the registers and main memory, Level 1 (L1), Level 2 (L2), and even L3 and L4 caches have been added. Typically the L1 cache is part of the processor (each core) and can store more data than the registers
18%
17.03.2021
, offices, and labs are not data centers and have power and cooling limitations. Standard wall sockets in the US are 120V, and common amperage values in the home are 15 and 20A. A 15A circuit has a capability
