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« Previous 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ... 55 Next »

18%
Parallelizing and memorizing Python programs with Joblib
20.05.2014
Home »  Archive  »  2014  »  Issue 20: IPv6...  » 
s remaining: 3.5s [Parallel(n_jobs=2)]: Done 600 out of 1000 | elapsed: 3.4s remaining: 2.3s [Parallel(n_jobs=2)]: Done 801 out of 1000 | elapsed: 4.5s remaining: 1.1s [Parallel
18%
networkd and nspawn in systemd
11.04.2016
Home »  Archive  »  2016  »  Issue 32: Measu...  » 
Lead Image © Kritiya Sumpun, 123RF.com
/etc/systemd/network Listings 2 and 3 show the two configuration files for the normal Ethernet card (Listing 2) and the bridge device (Listing 3). You can decide which device is configured
18%
Systemd network management and container handling
13.06.2016
Home »  Archive  »  2016  »  Issue 33: IPv6...  » 
Lead Image © Kritiya Sumpun, 123RF.com
/run/systemd/resolve/resolv.conf /etc/resolv.conf mkdir /etc/systemd/network Listings 2 and 3 show the two configuration files for the regular Ethernet card (Listing 2) and bridge device (Listing 3
18%
Persistent Memory
14.01.2016
Home »  HPC  »  Articles  » 
the registers and main memory, Level 1 (L1), Level 2 (L2), and even L3 and L4 caches have been added. Typically the L1 cache is part of the processor (each core) and can store more data than the registers
18%
Scalable network infrastructure in Layer 3 with BGP
14.08.2017
Home »  Archive  »  2017  »  Issue 40: Lean...  » 
Lead Image © artqu, 123RF.com
for your environments with Layer 3 tools. As long as two hosts have any kind of physical communication path, communication on Layer 3 works, even if the hosts in question reside in different Layer 2 segments ... Large environments such as clouds pose demands on the network, some of which cannot be met with Layer 2 solutions. The Border Gateway Protocol jumps into the breach in Layer 3 and ensures seamlessly ... Scalability in Layer 3 ... Scalable network infrastructure in Layer 3 with BGP
18%
How persistent memory will change computing
03.12.2015
Home »  Archive  »  2015  »  Issue 30: OpenD...  » 
Lead Image © rangizzz, 123RF.com
the registers and main memory, Level 1 (L1), Level 2 (L2), and even L3 and L4 caches have been added. Typically the L1 cache is part of the processor (each core) and can store more data than the registers
18%
Parallel Python with Joblib
08.04.2014
Home »  HPC  »  Articles  » 
[Parallel(n_jobs=2)]: Done 600 out of 1000 | elapsed: 3.4s remaining: 2.3s [Parallel(n_jobs=2)]: Done 801 out of 1000 | elapsed: 4.5s remaining: 1.1s [Parallel(n_jobs=2)]: Done 1000 out of 1000
18%
Virtual switching with Open vSwitch
28.07.2011
Home »  CloudAge  »  Articles  » 
 
10 [ ID] Interval Transfer Bandwidth 11 [ 3] 0.0 60.0 sec 5.80 GBytes 830 Mbits/sec You can now restrict the send performance. Note that the command expects you to enter the send ... 3
18%
Last Call for the ISC Student Cluster Competition
08.10.2013
Home »  HPC  »  News  » 
 
November 1, 2013 is the deadline for entries in International Supercomputing Conference (ISC '14) Student Cluster Competition. ISC '14 will be held in Leipzig, Germany on June 22-26, 2014
18%
US Army’s Excalibur System Solves 10 Billion Equations in 3 Minutes
18.06.2015
Home »  HPC  »  News  » 
 
XC40 before the system is placed into regular service. The Excalibur system comes with 101,184 processors, and the Stanford team had access to 22,00 of them. The team was working on a new scalability ... US Army’s Excalibur System Solves 10 Billion Equations in 3 Minutes

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